This application is based upon and claims priority from prior French Patent Application No. 99-04609, filed Apr. 13, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to digital signals, and more specifically to digital signal shaping for digital data transmissions between different units of data processing, instrumentation, or communications equipment.
2. Description of Related Art
A digital signal has the form of a voltage or current that alternates between two possible levels: a xe2x80x9chighxe2x80x9d level and a xe2x80x9clowxe2x80x9d level. A binary value (i.e., 0 or 1) is attributed to each of these two states. The transitions between the two levels of the signal form a corresponding series of binary values. This series of binary values carries information transmitted with the signal between a source and one or several reception points. The binary signals of a given protocol must conform to a specification which establishes their electrical characteristics such as the voltage or current levels that correspond to the logic values 0 and 1, the rise and fall times from one level to another, and the duration of a logic state. It is essential that the specification is rigorously complied with in order to correctly recognizing the exchanged data.
FIG. 1 shows a portion of a binary signal in the form of a voltage pulse (shown on the Y axis) that changes over time (shown on the X axis). An element of binary information 1 or 0 is represented by the presence of a voltage at the high level, which is determined by Vcc, or the low level, which is set at 0 V. These voltage levels must exist during predetermined time periods tH and tB, respectively. A transition from the low level to the high level (or xe2x80x9crising edgexe2x80x9d) takes a relatively short finite time tm. The same applies for the time td for a transition from the high level to the low level (or xe2x80x9cfalling edgexe2x80x9d). In the example of FIG. 1, the binary signal is symmetrical insofar as the times tH and tB of the high and low levels are identical, as are the transition times tm and td between those levels.
When a binary signal is to be transmitted by a cable over distances beyond a few centimeters, and possibly a few meters, the electrical characteristics of the cable in terms of resistance, capacitance, and induction, which are proportional to its length, create a load which tends to attenuate and modify the shape of the voltage or current waveforms. To prevent this phenomenon from causing a loss of transmission quality, it is required to send the binary signal through a relatively low impedance output stage which can switch rapidly between the levels. FIG. 2 shows an one such conventional output stage.
The output stage 10 includes an input terminal E which receives the binary signal before it is appropriately shaped for transmission along a line. For example, the binary input signal can come from a large-scale integration logic circuit. In general, the output stages of such circuits are not capable of driving a lossy transmission line. The purpose of the output stage is to apply this input signal onto the transmission line with a low output impedance. The input E is connected to a logic inverter 12 whose output is connected to each gate of first and second complementary MOS transistors 14 and 16. These transistors are connected in series between a supply voltage line Vcc and ground to form another inverter.
The first and second transistors 14 and 16 are PMOS and NMOS type transistors, respectively. The source of the first transistor 14 is connected to the voltage line Vcc and its drain is connected to the source of the second transistor 16. The drain of the second transistor 16 is connected to a 0 V (or ground) line. The output S of the output stage 10 is located at a connection node between the first and second transistors 14 and 16. This output S drives a transmission line 18 which exhibits a capacitive loss symbolized by a capacitor C1 (shown in dotted lines) that connects the transmission line 18 to ground.
The first and second transistors 14 and 16 are specially designed to deliver or absorb a high current. To this end, they possess a conduction channel of relatively large dimensions, which thus provides a low resistance. The presence of the logic inverter 12 serves to establish a double inversion of the digital signal supplied at the input (i.e., in combination with the inverter formed by transistors 14 and 16). As a result, the signals at the input E are reproduced with the same polarity at the output S. When the digital signal at the node NG connecting the gates of transistors 14 and 16 is at 0 V (which corresponds to a high level at input E), the second transistor 16 is OFF while the first transistor 14 is switched ON. Accordingly, the output S is connected to the supply voltage line Vcc via transistor 14. Conversely, when the digital signal at node NG is at the supply voltage level Vcc, the first transistor 14 is OFF and the second transistor 16 is switched ON. Thus, the output S is connected to ground via transistor 16.
The voltage level transitions at the output S (either to the high or to the low state) depend on the characteristics of the first 14 and second 16 transistors. In particular, these transistors determine the rise and fall times of the digital signal on the transmission line 18. Generally, it is desirable for the rise and fall times of the digital signal be the same (i.e., for the rising and falling edges of the signal to have the same shape as shown in FIG. 1). This implies identical characteristics for transistors 14 and 16, which are respectively of the PMOS and NMOS types. In particular, the critical characteristics are the switching thresholds of the transistors (i.e., the voltage level required to set the transistors into saturation) and the channel resistances.
However, in practice, PMOS and NMOS transistors cannot be rigorously identical with regard to these characteristics. In particular, the threshold voltage is determined at the fabrication stages, which are different depending on whether the transistor is a PMOS or NMOS transistor. Accordingly, the rising and falling edges cannot be perfectly symmetrical with an output stage of the type shown in FIG. 2. Moreover, in practice, there is a difference in the above-mentioned characteristics between two theoretically identical output stages 10 because of inevitable dispersions in the fabrication processes. This adds to the lack of symmetry due to the inherent differences between the PMOS and NMOS transistors when the digital signal is sent in the form of differential pairs. According to such a transmission mode, the digital data is sent on each of two transmission channels (for example, a pair of wires).
FIG. 3 shows the superposition of the theoretical shape of each signal of the digital signal pair of a differential pair transmission. These signals SP1 and SP2 are of mutually opposite levels, with one being fixed as the inverse of the other. In this example, the high and low levels of the signals are respectively at voltages Vcc and 0 V. A protocol establishes which of the two signals SP1 or SP2 is indexed to the logic levels of the transmitted data, and the other signal serves to establish the reference for the potential difference. The rising edges FA and the falling edges FD of the two signals are symmetrical, so their crossover points at the level transitions are always located at the median level (i.e., at xc2xd Vcc in this example).
Data transmission in the form of differential pairs occupies two channels instead of a single channel (e.g., as with a simple serial link), but provides good immunity against noise. Differential pair transmission is used for applications such as data processing for connecting peripherals between themselves or to a central processing unit. For example, there has recently been defined a transmission protocol that is refereed to as the universal serial bus (USB) for data busses that connect computer equipment hardware. Under the USB protocol, the digital signals are sent in the form of differential pairs. The USB is now being used in the field of personal computing and is intended to provide a universal platform for communication with the computer itself and peripherals such as a mouse, keyboard, printer, scanner, camera, speakers, and the like.
The USB scheme serves to provide an interface between a digital unit that is specially devised for the USB functions and the transmission cable. Such a functional unit is purely analog and serves to send digital signals with a waveform such as is set out in the USB specification (xe2x80x9cUniversal Serial Bus Revision 1.1, Chapter 7 xe2x80x9cElectrical Specificationxe2x80x9d, available on the Internet at xe2x80x9cwww.usb.orgxe2x80x9d). This specification establishes the operational signals (D+/Dxe2x88x92), the high and low levels, the rise and fall times, the crossover levels, the input levels, impedance matching, and so on. The USB specification sets out two transmission speeds: a low transmission speed (LOW SPEED) of 100 kbits/s and a high transmission speed (FULL SPEED) of 12 Mbits/s). The output signals must have a rise time of between 4 ns and 20 ns for full speed transfer, and between 75 ns and 300 ns for low speed transfer.
FIG. 4 shows the actual shape of the digital signals of FIG. 3 when they are processed by the output stage of FIG. 2. As shown, there is a first asymmetry between the rising edges FA and the falling edges FD of one signal SP1 or SP2 of the pair due to the characteristic differences between the PMOS and NMOS transistors of the individual output stages. This results in the crossover points of the two signals SP1 and SP2 being located at a voltage VCR which is staggered with respect to the median voltage level of xc2xd Vcc. Such a staggering is highly undesirable because it is a source of signal detection errors. Moreover, it decreases the noise immunity of the transmission line.
Additionally, each of the two signals SP1 and SP2 is produced by a separate output stage 10, which can introduce an additional asymmetry. For example, the signals SP1 and SP2 can exhibit differences at the level of their rising edges FA or falling edges FD. Further, as shown in FIG. 4, the signals SP1 and SP2 differ from the theoretical signals of FIG. 3 by the fact that the ends of the rising and falling edges FA and FD exhibit a continuous variation, and pass progressively from the transition state to the stationary state (high level or low level). This effect, which gives rise to a non-linearity of the edges, is due to the non-infinite switching speed of the transistors 14 and 16, and can generate a loss of transmission quality.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a digital signal output circuit that drives a data transmission line with good uniformity conditions, especially with regard to the symmetry between the rising and falling edges.
One embodiment of the present invention provides a digital signal output circuit that includes capacitor forming means connected as an integrator, charging means, discharging means, means for selectively coupling, and a digital signal output. The charging means selectively charges the capacitor forming means with a constant. charging current, and the discharging means selectively discharges the capacitor forming means with a constant discharging current. The means for selectively coupling selectively couples the capacitor forming means to the charging means and to the discharging means as a function of data to be transmitted by the digital signal. Additionally, the digital signal output is coupled to the capacitor forming means so as to establish a rising edge of the digital signal when the capacitor forming means is coupled to the charging means and a falling edge of the digital signal when the capacitor forming means is coupled to the discharging means. In a preferred embodiment, the constant charging current and the constant discharging current have the same magnitude so as to produce the digital signal with symmetrical rising and falling edges.
Another embodiment of the present invention provides a digital signal output circuit for outputting binary digital signals in the form of differential pairs on data transmission channels. The digital signal output circuit includes a pair of capacitor forming means connected as integrators, charging means, discharging means, means for selectively coupling, and a pair of digital signal outputs. The charging means selectively charges the capacitor forming means with a constant charging current, and the discharging means selectively discharges the capacitor forming means with a constant discharging current. The means for selectively coupling selectively couples the capacitor forming means to the charging means and to the discharging means as a function of data to be transmitted by the digital signal. Each of the digital signal outputs is coupled to one of the capacitor forming means so as to establish a rising edge at the digital signal output when the corresponding capacitor forming means is coupled to the charging means and a falling edge at the digital signal output when the corresponding capacitor forming means is coupled to the discharging means. In one preferred embodiment, the charging means and the discharging means are shared by the pair of digital signal outputs of the pair of data transmission channels, and one of the constant charging current and the constant discharging current is coupled to each of the digital signal outputs by switching means.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.